In recent years, as signal processing for higher level information is required, an integrated circuit is requested which enables to process the higher speed signals. Reduction in wiring length and improvement of the degree of the circuit integration have been achieved so as to reduce the wiring delay time as well as the superior transistor performance so as to make the operation speed of the integrated circuit higher.
Device performance improvement is basically obtained by the device size reduction. Improvement of the current gain cut-off frequency is obtained by reduction in the gate length in a field effect transistor. The superior performance of a transistor is achieved by reduction in the base thickness and the emitter width in a bipolar transistor, and reduction in the parasitic capacity caused by reducing periphery.
When the transistor is refined and improved in performance, the parasitic capacity of wiring in the chip will be a problem. Accordingly, in order to reduce the wiring delay time between the transistors, the wiring length is reduced and the large scale integration is achieved so that the speed of the integrated circuit may be increased.
However, it is impossible to reduce the length of all wires on the circuit layout. When the data signal rate of the data will be high frequency of several GHz the influence of the wiring length cannot also be ignored any more in reduced wiring. In order to reduce the delay time, low parasitic capacity air bridge wiring is used. However, the distortion is generated in a data signal due to an inductor component of wiring even if in the circuit.
As one kind of logic circuits, there is a flip-flop circuit able to express 1 bit information by the value of “0” and “1”, and hold the information. A flip-flop circuit is composed of a pair of switching elements basically. The information outputted from a flip-flop circuit is fed back to a flip-flop circuit itself, and is held as far as it is in the powered state.
FIG. 19 is an exemplary configuration of a flip-flop circuit 1 using an ECL basic circuit.
In FIG. 19, a master circuit 2 has a data reading circuit composed of resistance elements R1, R2, and transistors Q1, Q2, and Q18, and a data holding positive feedback circuit composed of resistance elements R1, R2, transistors Q3, Q4, Q9, transistors Q14, Q15, and resistance elements R5, R6. The master circuit 2 further has a current source circuit composed of a transistor Q12 connected to a common emitter of transistors Q18 and Q9.
A slave circuit 3 has a data reading circuit composed of resistance elements R3, R4, and transistors Q5, Q6, Q10, and a data holding positive feedback circuit composed of resistance elements R3, R4, transistors Q7, Q8, Q11, transistors Q16, Q17, and resistance elements R7, R8. The slave circuit 3 further has a current source circuit composed of a transistor Q16 connected to a common emitter of transistors Q10 and Q11.
GND is a ground terminal and VEE is a power supply terminal. Further, each of transistors Q14, Q15, resistance element R5 and R6, transistors Q16, Q17 and resistance elements R7, R8 composes emitter follower circuits. When an integrated circuit is formed with making the flip-flop circuit as the first stage circuit, the output of the flip-flop circuit 1 is composed of an emitter follower circuit. The emitter follower circuit composes a voltage level shift circuit of the data holding positive feedback circuit.
Due to the characteristic of the emitter follower circuit, even if the resistance values of the resistance elements R7 and R8 have been adjusted, the resistance elements R7 and R8 in the emitter follower circuit cannot perform as an output terminating resistance, and cannot obtain the impedance matching with the latter stage. In other words, it is difficult to form an output terminating resistance in the output of this emitter follower circuit, unlike in the case of a current switch differential circuit of FIG. 16 and FIG. 17 mentioned later, and a 2-to-1 selector core circuit of FIG. 18. Accordingly, it is difficult to get wide bandwidth impedance matching which covers up to tens of GHz with the latter stage in the circuit as it is.
As an optical receiving circuit, there is a transimpedance amplifier used to convert a low level electric current generated by a photodiode into a practical voltage signal.
A circuit exemplary configuration of the differential type transimpedance amplifier is shown in FIG. 20.
The differential type transimpedance amplifier of FIG. 20 has a differential amplifier circuit composed of transistors Q22 and Q23, load resistances R15 and R16 and a transistor Q24 for a constant current source. Moreover, the differential type transimpedance amplifier has an emitter follower circuit composed of transistors Q25 and Q26, and load resistances R19 and R20 connected to an output terminal of differential amplifier circuit. Moreover, the differential type transimpedance amplifier has feedback resisters R17 and R18 connected between the output terminal of the emitter follower circuit and the input terminal of the differential amplifier circuit mentioned above. GND represents a ground terminal and Vcc represents a power supply terminal.
When an integrated circuit is formed with making the transimpedance amplifier as the first stage circuit, the output of the transimpedance amplifier is composed of an emitter follower circuit.
Due to the characteristic of the emitter follower circuit, even if the resistance values of the resistance elements R19 and R20 have been adjusted, the resistance elements R19 and R20 in the emitter follower circuit cannot perform as an output terminating resistance, and cannot obtain the impedance matching with the latter stage. In other words, it is difficult to form an output terminating resistance in the output of this emitter follower circuit, unlike in the case of a current switch differential circuit of FIG. 16 and FIG. 17 mentioned later, and a 2-to-1 selector core circuit of FIG. 18. Accordingly, it is difficult to get wide bandwidth impedance matching by a circuit with no change.
A semiconductor integrated circuit having current switch differential circuits as shown in FIG. 16 and FIG. 17, and an emitter follower circuits to which the output of the current switch differential circuits input is disclosed in the patent document 1 as a related art. In FIG. 16 and FIG. 17, an output terminal of current switch differential circuit 13 and an input terminal of an emitter follower circuit are connected via wiring 5 and 6. The circuit is composed so that the characteristic impedance of the wiring 5 and 6 may be matched with the output impedance of the current switch differential circuit 13 or the input impedance of the emitter follower circuit 14 in the predetermined frequency range respectively. The patent document 1 discloses that it is possible to suppress the distortion occurrence of the data signal and the gain peaking of the frequency characteristic by the technology of the patent document 1.
Further, in the patent document 2, a technology is disclosed with which a transmission line on the mounting board performs the impedance matching with the input and the output of an IC chip and the output drive current of an IC chip can be reduced so that the signal reflection and loss do not occur to even if the operation speed becomes high. Thus, it is enabled to provide a semiconductor apparatus with high speed and the low power consumption by the technology described in the patent document 2.
A driver IC in which a 2-to-1 selector and a differential distribution type amplifier are integrated as shown in FIG. 18 is disclosed in a non-patent document 1. A wide bandwidth impedance matching is performed between the 2-to-1 selector core circuit 15 and the differential distribution type amplifier 11. Load resistances R1 and R2 of the 2-to-1 selector core circuit 15 are used as an output terminating resistance of the first stage circuit, and the input matching resistances R21 and R22 of the differential distribution type amplifier are used as an input terminating resistance of the latter stage circuit. The characteristic impedance of the wiring 5 and 6 between the 2-to-1 selector core circuit 15 and the differential distribution type amplifier 11 has been matched with the input impedance of the differential distribution type amplifier of the latter stage circuit. As a result, the input impedance of the differential distribution type amplifier of the latter stage connected by wiring becomes flat from DC (Direct Current) to 80 GHz, and the distortion occurrence of the data signal in wiring has been suppressed.